Added bzip2 lib and Quake (thanks to Lubomyr)
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pelya
156
project/jni/application/quake/source/cpu.c
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156
project/jni/application/quake/source/cpu.c
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/*
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <sys/mman.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "cpu.h"
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/* Define this to the CPU frequency */
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#define CPU_FREQ 336000000 /* CPU clock: 336 MHz */
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#define CFG_EXTAL 12000000 /* EXT clock: 12 Mhz */
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// SDRAM Timings, unit: ns
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#define SDRAM_TRAS 45 /* RAS# Active Time */
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#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
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#define SDRAM_TPC 20 /* RAS# Precharge Time */
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#define SDRAM_TRWL 7 /* Write Latency Time */
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#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
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//#define SDRAM_TREF 7812 /* Refresh period: 8192 refresh cycles/64ms */
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#include "jz4740.h"
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static unsigned long jz_dev=0;
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static volatile unsigned long *jz_cpmregl, *jz_emcregl;
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volatile unsigned short *jz_emcregs;
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static inline int sdram_convert(unsigned int pllin,unsigned int *sdram_freq)
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{
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register unsigned int ns, tmp;
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ns = 1000000000 / pllin;
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/* Set refresh registers */
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tmp = SDRAM_TREF/ns;
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tmp = tmp/64 + 1;
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if (tmp > 0xff) tmp = 0xff;
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*sdram_freq = tmp;
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return 0;
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}
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static int
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pll_init(unsigned int clock)
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{
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register unsigned int cfcr, plcr1;
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unsigned int sdramclock = 0;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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//int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:L:M */
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int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
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int nf, pllout2;
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cfcr = CPM_CPCCR_CLKOEN |
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(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? clock : (clock / 2);
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/* Init UHC clock */
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// REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
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jz_cpmregl[0x6C>>2] = pllout2 / 48000000 - 1;
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nf = clock * 2 / CFG_EXTAL;
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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// REG_CPM_CPCCR = cfcr;
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// REG_CPM_CPPCR = plcr1;
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jz_cpmregl[0] = cfcr;
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jz_cpmregl[0x10>>2] = plcr1;
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sdram_convert(clock,&sdramclock);
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if (sdramclock > 0) {
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// REG_EMC_RTCOR = sdramclock;
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// REG_EMC_RTCNT = sdramclock;
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jz_emcregs[0x8C>>1] = sdramclock;
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jz_emcregs[0x88>>1] = sdramclock;
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}
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}
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void
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cpu_init()
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{
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jz_dev = open("/dev/mem", O_RDWR);
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jz_cpmregl=(unsigned long *)mmap(0, 0x80, PROT_READ|PROT_WRITE, MAP_SHARED, jz_dev, 0x10000000);
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jz_emcregl=(unsigned long *)mmap(0, 0x90, PROT_READ|PROT_WRITE, MAP_SHARED, jz_dev, 0x13010000);
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jz_emcregs=(unsigned short *)jz_emcregl;
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}
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void
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cpu_deinit()
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{
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cpu_set_clock( GP2X_MAX_CLOCK );
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munmap((void *)jz_cpmregl, 0x80);
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munmap((void *)jz_emcregl, 0x90);
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close(jz_dev);
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// fcloseall();
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sync();
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}
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static void
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loc_set_clock(int clock_in_mhz )
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{
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if (clock_in_mhz >= GP2X_MIN_CLOCK && clock_in_mhz <= GP2X_MAX_CLOCK) {
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pll_init( clock_in_mhz * 1000000 );
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}
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}
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static unsigned int loc_clock_in_mhz = GP2X_DEF_CLOCK;
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void
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cpu_set_clock(unsigned int clock_in_mhz)
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{
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if (clock_in_mhz == loc_clock_in_mhz) return;
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loc_clock_in_mhz = clock_in_mhz;
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loc_set_clock(clock_in_mhz);
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return;
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}
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unsigned int
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cpu_get_clock()
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{
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return loc_clock_in_mhz;
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}
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